1. Field of the Invention
The present invention is related to a semiconductor device and a manufacturing method thereof, and particularly to an electrode structure of a memory capacitor and a method of manufacturing the same.
2. Description of Related Art
As technology advances, application of semiconductor devices is growing more and more extensive. For example, semiconductor memory devices such as dynamic random access memory (DRAM) devices or static random access memory (SRAM) devices generally include capacitors and transistors to store and read data or information. Given that the memory capacity required by computers increases rapidly, the number of capacitors required and the required capacity of each capacitor also increases as well. Therefore, the semiconductor manufacturing technology needs to change its process technology to satisfy such demands.
Meanwhile, to further enhance the integration level in the DRAM, the manufacturing process thereof continues miniaturizing and a capacitor cross section area per unit and space among capacitors keep growing smaller and smaller. Within such limited space, capacitors need to provide sufficient capacity to maintain signal intensity. Hence, in DRAM designs, the interrelation between the design and layout of a capacitor structure and capacity thereof is emphasized and the manufacturing process of DRAMs is simplified to enhance yield and reduce fabrication costs for DRAM manufacturers.
DRAMs use capacitors as a device for storing signals. The more charges a capacitor stores, the less reading data is affected by noise, and the frequency of refreshing may thus be further reduced. Methods of increasing capacity of the capacitor include: (1) increasing the dielectric constant of the dielectric layer to increase the number of charges stored by each unit area of the capacitor; (2) reducing the thickness of the dielectric layer although the quality level of the dielectric material itself would limit the thickness of the dielectric layer only to a certain minimum value; (3) increasing the area of the capacitor so that the number of charges stored in the capacitor increases although the integration level in the DRAM would thus be reduced.
When the storage capacity of the conventional DRAM is smaller, in the integrated circuit process, two-dimensional capacitors are mainly used for implementation, i.e. the so-called planar type capacitors. The planar type capacitor needs to occupy a considerable area of a semiconductor substrate to store charges and therefore is not suitable to be applied in high integration levels. DRAMs with high integration levels need to use three-dimensional capacitors for implementation, such as the so-called stack type capacitor or trench type capacitor. When integration of memory devices reaches higher levels, a simple three-dimensional capacitor structure is not sufficient for its purposes. Consequently, a solution of increasing the surface area of the DRAM within a small area is thus developed.
Furthermore, in order to effectively increase capacity, the cylindrical capacitor having a larger total surface area on an interior and an exterior side is chosen over the conventional cup capacitor which is more stable although twin bit failure may occur if intensity of the capacitor structure weakens. For example, during the 90 nm fabrication process, twin bit failure may occur because the capacitor structure is unstable. Accordingly, solutions point in two directions. On the one aspect, space in the capacitor structure is designed as such to actively avoid contact between capacitors. On the other aspect, support structures are added among capacitors during steps in the fabrication process to passively prevent the twin bit failure from occurring.
Several US patents or published patent applications disclose techniques which increase the capacitor surface area by different exterior designs. In U.S. Pat. No. 5,656,536, a coronary electrode extending inwards is used to increase the capacitor surface area. In U.S. Pat. No. 5,763,286, a lower electrode plate having an interior surface and an exterior surface as an annular trench is used to increase the capacitor surface area. Moreover, in U.S. Pat. No. 6,177,309, a cylinder having a dual annular section is used as a lower electrode plate to increase the capacitor surface area. In U.S. Pat. No. 7,119,392, a heavily doped amorphous silicon and a lightly doped amorphous silicon are used to enhance the intensity of the structure and a hemispherical grain (HSG) is used as a storage node to increase the capacitor surface area.